Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Springer | 2008 | ISBN: 0387764739 | 302 pages | PDF | 13 MB
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.